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- W3081551657 abstract "In this work, sub-10 nm high-k dielectric Silicon-on-Insulator (SOI) FinFET has been investigated for high-performance analog applications with a very low power supply. The performance analysis of 9 nm gate length high-k SOI-FinFET has been compared with conventional FinFET. It has been evaluated that the proposed device provides better solutions in terms of better subthreshold slope, lowering of threshold voltage, device efficiency, and higher switching ratio (I <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</inf> /I <inf xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>off</inf> ratio). Thus, the high-k dielectric SOI-FinFET device paves the way for high-performance switching applications." @default.
- W3081551657 created "2020-09-08" @default.
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- W3081551657 date "2020-03-01" @default.
- W3081551657 modified "2023-09-27" @default.
- W3081551657 title "Sub-10 nm High-k Dielectric SOI-FinFET for HighPerformance Low Power Applications" @default.
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- W3081551657 doi "https://doi.org/10.1109/icsc48311.2020.9182748" @default.
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