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- W3082245812 abstract "Due to increase in demand for low power electronic systems in recent years, significant research and development work is happening in the low power domain. This is especially true for Field Programmable Gate Arrays (FPGAs), which dissipate significantly more power than fixed-logic implementations. Power is a critical issue when FPGA applications are considered. In spite of the significant improvements in the recent past, power dissipation in FPGAs is significant. With the scaling down of CMOS process technology, factors like higher total interconnect capacitance per chip, higher operating frequencies, and increase in leakage will continue to increase the power density. All these factors will increase the operating temperature of the device which leads to the production of heat inside the chip. The final implementation is affected by the problems associated with the increase in heat produced. Some critical issues associated with temperature rise are the system reliability, the packaging of the chip and the life cycle of the final product. The dominance of the heat problem is one of the key design issues, which needs to be addressed. It is observed that in FPGAs the central portion of the device gets heated up due to the concentration of active Configurable Logic Blocks (CLBs) at the centre. Effect of arranging the unused CLBs at different places across the FPGA and the thermal distribution is examined in the present work. This paper aims at minimizing the total power consumption and also to redistribute it across the entire FPGA. A temperature-aware placement and routing is considered, by placing the unused CLBs across different locations of the FPGA so as to obtain uniform temperature profile across the entire cross section of FPGA. Since temperature is dependent on the switching activity of the hardware resources of FPGA, the proposed methodology aims at redistributing the switching activity over the FPGA resources." @default.
- W3082245812 created "2020-09-08" @default.
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- W3082245812 date "2020-07-01" @default.
- W3082245812 modified "2023-09-27" @default.
- W3082245812 title "Power Management in FPGAs using a Temperature Aware Place and Route Methodology" @default.
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- W3082245812 doi "https://doi.org/10.1109/iccsp48568.2020.9182209" @default.
- W3082245812 hasPublicationYear "2020" @default.
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