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- W3084964196 abstract "Configurable architectures are alternatives to attend the quality and energy requirements of image and video processing dynamically. Together with approximate computing techniques, these approaches allow for energy-efficient digital systems regarding the error-tolerant applications. This paper proposes a fine-grained methodology to deal with multiple power-performance-quality requirements needed in nowadays digital Complementary Metal-Oxide-Semiconductor (CMOS) design. The main objectives can be observed as follows: i) to perform a design-space exploration through the bit-width reduction of the 2D Gaussian filter, ii) to develop approximate 2D Gaussian filter architectures during the design-time which serves as a proof of concept, and iii) to design a run-time accuracy-configurable 2D Gaussian filter accelerator. The application quality analysis is performed by adopting scripts coded in Python language. All the design-time approximate plus the accuracy-configurable architectures were described in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized for Application Specific Integrated Circuit (ASIC) implementation. The results for a 65nm cell-based technology show energy per operation reductions ranging from 9.87% to 59% with bit widths ranging from 7 to 3 bits, respectively. The extra hardware components to ensure the run-time configurable behavior implies up to 14% of area increasing." @default.
- W3084964196 created "2020-09-21" @default.
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- W3084964196 date "2020-08-01" @default.
- W3084964196 modified "2023-10-07" @default.
- W3084964196 title "A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design" @default.
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- W3084964196 doi "https://doi.org/10.1109/sbcci50935.2020.9189912" @default.
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