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- W3085806110 abstract "This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns." @default.
- W3085806110 created "2020-09-21" @default.
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- W3085806110 date "2020-08-01" @default.
- W3085806110 modified "2023-10-14" @default.
- W3085806110 title "Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier" @default.
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- W3085806110 doi "https://doi.org/10.1109/sbcci50935.2020.9189918" @default.
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