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- W3089592056 abstract "A referenceless single-loop clock and data recovery (CDR) with a 6.4-11-Gb/s capture range is presented. A dynamic bandwidth control (DBWC) technique for reducing the frequency-acquisition time and adaptive loop gain control (ALGC) for optimizing the jitter tolerance are described in detail. In addition, a cycle-slip detector (CSDET) with a consecutive-edge selector (CES) is proposed to improve the accuracy of the frequency detection. Fabricated in a 28-nm CMOS process, the proposed CDR has a frequency-acquisition time that is reduced by approximately 30% with the DBWC technique enabled. Also, the capture range is expanded by 1.1 Gb/s compared to the prior work due to improvement of the CSDET. The proposed ALGC technique based on jitter estimation is demonstrated with JTOL test results using PRBS15 input data with 0.28-UIPP random jitter and 1-100 MHz sinusoidal jitter." @default.
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- W3089592056 date "2020-01-01" @default.
- W3089592056 modified "2023-10-06" @default.
- W3089592056 title "A 6.4–11 Gb/s Wide-Range Referenceless Single-Loop CDR With Adaptive JTOL" @default.
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- W3089592056 doi "https://doi.org/10.1109/lssc.2020.3027021" @default.
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