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- W3090239488 abstract "A recently proposed TRAnsistor-level Programmable (TRAP) fabric can enable seamless on-die integration of high-density reconfigurable logic with custom ICs. However, state-of-the-art CAD tools are developed for either ASICs or FPGAs and do not support the new architecture. To this end, we present CASPER − a novel CAD framework for implementing designs on the TRAP fabric. CASPER begins with characterizing an ASIC-esque cell library in order to leverage the industry-leading logic synthesis tools for TRAP. We then systematically remodel the TimberWolf and the Versatile Place and Route (VPR) tools to facilitate TRAP-specific design placement and routing, respectively. In addition, we develop a robust programming bitstream generation tool for TRAP. Lastly, we fabricate a 65nm prototype TRAP chip and implement ten ISCAS-85/MCNC benchmark circuits on it. Our evaluation results validate the proposed CAD framework and provide a comparative overhead analysis between TRAP and FPGA." @default.
- W3090239488 created "2020-10-08" @default.
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- W3090239488 date "2020-10-01" @default.
- W3090239488 modified "2023-09-27" @default.
- W3090239488 title "CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric" @default.
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- W3090239488 doi "https://doi.org/10.1109/iscas45731.2020.9181074" @default.
- W3090239488 hasPublicationYear "2020" @default.
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