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- W3093653196 abstract "The Piccolo block cipher is a lightweight block encryption for hardware use. Hardware devices are equipped with limited computation resources and small memory. In this paper, we propose an implementation to carry out through several trade-offs between area and speed. We implemented the Piccolo block cipher algorithm with 128-bit key in two different architectures on FPGA: the iterative and the 4-bit serial architectures. The proposed implementation was performed on Xilinx Spartan-3. The iterative implementation achieves 76% of resource utilization. This implementation takes 31 clock cycles to perform the encryption or decryption. So, it results in a throughput of 151.1 Mbps. The serial implementation was optimized in terms of area to reduce the cost. It achieves 54% of resource utilization and takes 496 clock cycles resulting in a throughput of 6.39 Mbps." @default.
- W3093653196 created "2020-10-29" @default.
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- W3093653196 date "2020-09-01" @default.
- W3093653196 modified "2023-09-27" @default.
- W3093653196 title "Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA" @default.
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- W3093653196 doi "https://doi.org/10.1109/atsip49331.2020.9231586" @default.
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