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- W3095339265 abstract "This paper presents a design strategy to reduce the impact of process variations and soft error susceptibility in FinFET circuits. The mitigation is provided by connecting a Schmitt Trigger at the logic gate output. The improvements in power and delay variability can reach up to 32.6% and 42.1%, respectively, with logic cells almost immune to soft error even at the near-threshold regime. When compared with other circuit-level methods such as sleep transistor, decoupling cells, and transistor reordering, on average, the Schmitt Trigger technique is at least 6%, 8%, and 10.5% more robust to process variability, respectively. • Explore circuit-level approaches in FinFET designs to mitigate process variability and soft errors. • The improvement in power and delay variability can reach to 32.6% and 42.1%, respectively, using the Schmitt Trigger design. • A circuit design using Schmitt Trigger is immune to soft errors even at the near-threshold regime. • Larger Schmitt Triggers decrease the impact on power variability considerably. • The Schmitt Trigger is more advisable for designs with huge reliability concerns due to overhead in area, delay, and power." @default.
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- W3095339265 date "2020-11-01" @default.
- W3095339265 modified "2023-10-13" @default.
- W3095339265 title "Circuit design using Schmitt Trigger to reliability improvement" @default.
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- W3095339265 doi "https://doi.org/10.1016/j.microrel.2020.113754" @default.
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