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• W3095684001 abstract "In the past years, we have seen a tremendous increase in small and battery-powered devicesfor sensing, wireless communication, data processing, classification, and recognition tasks.Collectively referred to as the Internet of Things (IoT), all these devices have a huge impact onseveral aspects of our day-to-day life. Since IoT devices need to be portable and lightweight,they depend on battery or environmental harvested-energy as their primary energy source.As a result, IoT devices have to operate on a limited energy envelope in order to increasethe supply duration of their energy source. In order to meet the stringent energy-budget ofbattery-powered IoT devices, extreme-low energy design has become a standard requirement.In this regard, supply voltage downscaling has been used as an effective approach for reducingthe energy consumption of Complementary Metal Oxide Semiconductor (CMOS) circuits andenable ultra-low power operation. Although aggressive supply voltage downscaling is a popularapproach for extreme-low power operation, it reduces the performance significantly. In thisregard, operating in the near-threshold voltage domain (commonly known as NTC) couldprovide a better trade-off between performance and energy saving, as it can achieve up to 10×energy-saving at the cost of linear performance reduction. However, the broad applicabilityof NTC is hindered by several barriers, such as the increase in functional failure of memorycomponents, performance variation, and higher sensitivity to variation effects.For NTC processors, wide variation extent and higher functional failure rate pose a dauntingchallenge to assure timing certainty of logic blocks such as pipeline stages of a processor coreand stability of memory elements (caches and registers). Moreover, due to the reduction innoise margin of memory components, susceptibility to runtime reliability issues, such as agingand soft errors, is also increasing with supply voltage downscaling. These challenges limit NTCpotentials and force designers to use large timing margins in order to ensure reliable operationof different architectural blocks, which leads to significant overheads. Therefore, analyzing andmitigating variation induced timing failure of pipeline stages and memory failures during earlydesign phases plays a crucial role in the design of resilient and energy-efficient microprocessorarchitectures.This thesis provides cost-effective cross-layer solutions to improve the resiliency and energy-efficiency of energy-constrained pipelined microprocessors operating in the near-threshold volt-age domain. Different architecture-level solutions for logic and memory components of apipelined processor are presented in this thesis. The solutions provided in this thesis addressthe three main NTC challenges, namely increase in sensitivity to process variation, highermemory failure rate, and performance uncertainties. Additionally, this thesis demonstrateshow to exploit emerging computing paradigms, such as approximate computing, in order tofurther improve the energy efficiency of NTC designs." @default.
• W3095684001 created "2020-11-09" @default.
• W3095684001 creator A5020422864 @default.
• W3095684001 date "2019-01-01" @default.
• W3095684001 modified "2023-09-23" @default.
• W3095684001 title "Resilient Energy-Constrained Microprocessor Architectures" @default.
• W3095684001 doi "https://doi.org/10.5445/ir/1000094270" @default.
• W3095684001 hasPublicationYear "2019" @default.
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