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- W3096129436 abstract "We present the design principles and circuit details of a single-bit continuous-time delta-sigma ADC that achieves 13.3-bit resolution over a 20-MHz signal bandwidth. The modulator, which operates at a sampling rate of 2.56 GHz in a 65-nm CMOS process, uses a 2 $times $ time-interleaved ADC to address the problem of comparator metastability. A 4 $times $ time-interleaved virtual-ground-switched resistive FIR feedback DAC is used for low distortion and power-efficient operation. Interleaving artifacts caused by DAC-element mismatch are addressed by mixed-signal calibration, which is enabled by the DAC architecture. The decimator is implemented using poly-phase techniques. A prototype modulator, which operates with a 1.1-V supply, achieves 82.1-dB peak SNDR and THD of 98.6 dBc while consuming 11.3 mW. The resulting Schreier FoM is 174.1 dB. The decimator dissipates 13.5 mW." @default.
- W3096129436 created "2020-11-09" @default.
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- W3096129436 date "2021-03-01" @default.
- W3096129436 modified "2023-10-14" @default.
- W3096129436 title "Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback" @default.
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- W3096129436 doi "https://doi.org/10.1109/jssc.2020.3025573" @default.
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