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- W3097964456 abstract "Performance and energy figures of Deep Neural Network (DNN) accelerators are profoundly affected by the communication and memory sub-system. In this paper, we make the case of a state-of-the-art multi-chip-module-based architecture for DNN inference acceleration. We propose a hybrid wired/wireless network-in-package interconnection fabric and a compression technique for drastically improving the communication efficiency and reducing the memory and communication traffic with a consequent improvement of performance and energy metrics. We assess the inference performance and energy improvement vs. accuracy degradation for different CNNs showing that up to 77% and 68% of inference latency reduction and inference energy reduction, respectively, can be obtained while keeping the accuracy degradation below 5% as respect to the original uncompressed CNN." @default.
- W3097964456 created "2020-11-09" @default.
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- W3097964456 date "2020-09-24" @default.
- W3097964456 modified "2023-09-25" @default.
- W3097964456 title "Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression" @default.
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- W3097964456 doi "https://doi.org/10.1109/nocs50636.2020.9241714" @default.
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