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• W3100324275 endingPage "1968" @default.
• W3100324275 startingPage "1968" @default.
• W3100324275 abstract "A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm2 on silicon." @default.
• W3100324275 created "2020-11-23" @default.
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• W3100324275 date "2020-11-21" @default.
• W3100324275 modified "2023-10-16" @default.
• W3100324275 title "A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS" @default.
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• W3100324275 doi "https://doi.org/10.3390/electronics9111968" @default.
• W3100324275 hasPublicationYear "2020" @default.
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