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- W3106803497 abstract "Full adder is the heart of any central processing unit that is a core component employed in all the processors. This paper presents a design methodology for full adder circuit with minimum number of transistor i.e. reduced size & reduced area. This is then used to implement 10T full adder design for carrying out summation of bits. The analysis of the developed full adder design is done at room temperature CMOS 90 nm and 180 nm technologies using Micro wind tool 2.6.The result shows the comparison between different CMOS technologies in 90 nm and 180 nm using micro wind tool 2.6 on the design in regards of power dissipation, propagation delay and power delay product. A comparison table shown having power, delay and transistor count based comparison at 90 nm and 180 nm technologies showing delay in time and dissipated Power within the full adder summation circuit design at room temperatures. We will also provide the layout of the full adder design at both technologies. The proposed technique shows 96.66% less power consumption in 90 nm and 93.93% less power consumption in 180nm as compare to base paper hybrid logic design." @default.
- W3106803497 created "2020-12-07" @default.
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- W3106803497 date "2020-01-01" @default.
- W3106803497 modified "2023-09-27" @default.
- W3106803497 title "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT" @default.
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