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- W3107798402 abstract "A two-stage 24-30 GHz wideband power amplifier (PA) with an adaptive capacitance linearizer is presented, which is fabricated using a 28-nm bulk CMOS process. Staggered input gain matchings of the driver and power stages are implemented with wideband output power matchings to achieve wideband power characteristics. An adaptive capacitance linearizer is introduced at the power stage input to improve the AM-PM linearity with respect to input powers. At 24/26/28/30 GHz, it achieves 19.7/20.3/20/20 dBm P <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>sat</sub> , 18.2/18.2/17.8/17.2 dBm P <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>1dB</sub> , and 34.5/33.1/30/30.3% peak power added efficiency (PAE). The small-signal gain of 21.2 dB and the 3-dB bandwidth of 8.2 GHz are achieved. It has a core size of 0.189 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> ." @default.
- W3107798402 created "2020-12-07" @default.
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- W3107798402 date "2021-04-01" @default.
- W3107798402 modified "2023-10-06" @default.
- W3107798402 title "A 24–30 GHz 31.7% Fractional Bandwidth Power Amplifier With an Adaptive Capacitance Linearizer" @default.
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- W3107798402 doi "https://doi.org/10.1109/tcsii.2020.3036645" @default.
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