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• W3109152005 abstract "STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-based on-chip memories. While STT-MRAM memories benefit from ultra-low leakage power and high density, they suffer from some reliability challenges, namely, read disturbance, write failure, and retention failure. The write failure; storing a wrong value in an STT-MRAM cell during a write operation, is the most crucial reliability challenge. In this article, we propose ROCKY; a robust architecture equipped with efficient replacement policies for STT-MRAM-based cache memory hierarchy to improve the robustness of STT-MRAM part against the write failures. ROCKY reduces susceptible transitions in STT-MRAM cache memories leading to more reliable STT-MRAM write operations. The simulation results through comparison with traditional cache memory hierarchy demonstrate ROCKY decreases the WER of STT-MRAM cache memories by up to 35.4 percent while imposing less than 1 percent performance overhead to the system." @default.
• W3109152005 created "2020-12-07" @default.
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• W3109152005 date "2020-01-01" @default.
• W3109152005 modified "2023-09-24" @default.
• W3109152005 title "ROCKY: A Robust Hybrid On-chip Memory Kit For The Processors With STT-MRAM Cache Technology" @default.
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• W3109152005 doi "https://doi.org/10.1109/tc.2020.3040152" @default.
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