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- W3110156328 abstract "In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure two- or three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications." @default.
- W3110156328 created "2020-12-07" @default.
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- W3110156328 date "2021-01-01" @default.
- W3110156328 modified "2023-09-25" @default.
- W3110156328 title "Design of CMOS three-stage amplifiers for near-to-minimum settling-time" @default.
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- W3110156328 doi "https://doi.org/10.1016/j.mejo.2020.104939" @default.
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