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• W3110255261 abstract "To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given." @default.
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• W3110255261 date "2019-10-14" @default.
• W3110255261 modified "2023-09-26" @default.
• W3110255261 title "Laser Processing For 3D Junctionless Transistor Fabrication" @default.
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