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• W3112302017 abstract "On-chip signal routing has become an issue of growing importance in modern VLSI complexity single flux quantum (SFQ) systems. In this paper, different routing methods for these systems are described. The routing methods include either passive transmission lines (PTLs) or Josephson transmission lines (JTLs) as interconnects. Driving multiple SFQ gates is also a challenging issue in automated layout and clock tree synthesis (CTS) due to the limited fanout of SFQ gates. To support multiple fanout, splitters are used to distribute multiple SFQ pulses. These splitters require significant area, delay, and power. In this paper, several area and power efficient splitters are proposed for large scale SFQ integrated circuits. A primary issue within a long SFQ interconnect is resonance effects due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology for long interconnect to reduce and manage these resonance effects is also described. Summarizing, guidelines and tradeoffs appropriate for automated layout and synthesis are described for driving long and short interconnect in VLSI complexity SFQ systems." @default.
• W3112302017 created "2020-12-21" @default.
• W3112302017 creator A5003920747 @default.
• W3112302017 creator A5053517349 @default.
• W3112302017 date "2020-11-05" @default.
• W3112302017 modified "2023-10-18" @default.
• W3112302017 title "Global interconnects in VLSI complexity single flux quantum systems" @default.
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• W3112302017 doi "https://doi.org/10.1145/3414622.3431911" @default.
• W3112302017 hasPublicationYear "2020" @default.
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