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• W3113256013 abstract "Resistive random access memory (RRAM)-based compute-in-memory architecture helps overcome the bottleneck caused by large memory transactions in the convolutional neural network (CNN) accelerators. However, their deployment using 2-D IC technology faces challenges, as today's RRAM cells remain at legacy nodes above 20 nm due to high programming voltages. Besides, power-hungry analog-to-digital converter (ADC) units limit the throughput of RRAM accelerators. In this article, we present the first-ever heterogeneous (multiple technology nodes) mixed-signal monolithic 3-D IC designs of the RRAM CNN accelerator. Our RRAM remains at legacy 40-nm nodes in one tier, but CMOS periphery scales toward advanced 28/16 nm in another tier. Our 3-D designs overcome the bottleneck caused by ADCs and offer up to 4.9× improvement in energy efficiency in TOPS/W and up to 50% reduction in footprint area over 40-nm 2-D IC designs. Compared with existing 2-D works, our 3-D architecture offers up to 28.6× improvement in energy efficiency." @default.
• W3113256013 created "2020-12-21" @default.
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• W3113256013 date "2021-02-01" @default.
• W3113256013 modified "2023-10-06" @default.
• W3113256013 title "Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM" @default.
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• W3113256013 doi "https://doi.org/10.1109/tvlsi.2020.3042411" @default.
• W3113256013 hasPublicationYear "2021" @default.
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