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• W3113471851 abstract "A proactive clock-gating system (PCGS) in a 7-nm Qualcomm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>®</sup> Hexagon™ digital signal processor (DSP) improves performance or energy efficiency by reducing the magnitude of supply voltage ( V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> ) droops. The PCGS integrates a digital power meter (DPM) to monitor the power per cycle based on microarchitectural events and a voltage-clock-gating (VCG) circuit with a power-delivery-network (PDN) model to predict the V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> response to DPM power changes. When the PDN model anticipates a potential V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> -droop violation, the VCG adapts the clock frequency ( F <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>CLK</sub> ) by gating the global clock to reduce the actual V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> -droop magnitude. Silicon measurements of the PCGS in the 7-nm DSP demonstrate a 10% higher F <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>CLK</sub> or 5% lower V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DD</sub> ." @default.
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• W3113471851 date "2021-04-01" @default.
• W3113471851 modified "2023-09-27" @default.
• W3113471851 title "A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor" @default.
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• W3113471851 doi "https://doi.org/10.1109/jssc.2020.3043786" @default.
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