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• W3114688520 abstract "We describe a programmable and scalable Convolutional Neural Network (CNN) hardware accelerator optimized for mobile and edge inference computing. The accelerator is comprised of 4 heterogeneous engines - input engine, filter engine, post processing engine, and output engine. The specialized engines execute independently and concurrently. All engines have a core set of common instructions with each engine further specialized for specific functions. We describe the operation of each engine and provide silicon validated results for a number of CNN networks including LeNet-5, TinySSD, and SqueezeNet. We describe a blind modulation detection application using SqueezeNet. The accelerator has been fabricated in 28nm CMOS and runs at 1GHz. The logic consumes 0.6 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and the fully hardened core with 2MB of SRAM including built-in self-test consumes 9.36mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . The accelerator's filter engine implements 288 f16 multipliers thereby achieving 288 GFLOPS at 1GHz. Two TOPS of peak performance is achieved with all engines running in parallel. The accelerator including SRAM dissipates 193mW running LeNet-5 at room temperature." @default.
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• W3114688520 date "2020-10-21" @default.
• W3114688520 modified "2023-10-14" @default.
• W3114688520 title "Heterogeneous Edge CNN Hardware Accelerator" @default.
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• W3114688520 doi "https://doi.org/10.1109/wcsp49889.2020.9299736" @default.
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