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- W3115221831 abstract "With advances in technology, the number of transistors in the chip increases resulting in large increase in the power budget. The increasing power budgets prohibit these devices being used in the design. Voltage scaling has been proven to be very effective to decrease power consumption. Near threshold design is a powerful knob for improving energy efficiency and to reduce the power density in the integrated chips. In near threshold region, the supply voltage is approximately equal to the threshold voltage of the transistors. Near threshold computing promises improved energy efficiency, but it is more sensitive to parametric variations compared to conventional super threshold operations. Therefore, it is very critical to develop optimized standard cells for near threshold operation to improve the energy efficiency and variability characteristics. This paper explores the importance of optimized standard cell design to reduce the delay, power consumption, and variability issues of digital circuits and compares various standard cell optimization techniques for ultra-low power applications from recent literatures. Near threshold design is best suited to energy and performance constrained intelligent edge devices for Internet of things applications." @default.
- W3115221831 created "2021-01-05" @default.
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- W3115221831 date "2020-11-05" @default.
- W3115221831 modified "2023-09-25" @default.
- W3115221831 title "Standard Cell Optimization Techniques for Near Threshold Computing – A Review" @default.
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- W3115221831 doi "https://doi.org/10.1109/iceca49313.2020.9297602" @default.
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