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- W3116610080 abstract "Three-dimensional (3D) microsystem integration offers solutions for improved device functionality, increased bandwidth per volume, simplified design and assembly, and system miniaturization. Through-silicon vias (TSVs) are a key technology for incorporating devices into 3D integration schemes. Microelectromechanical systems (MEMS) applications often utilize full thickness silicon substrates, creating a need for mesoscale TSVs (> 0.5 mm thick) at high aspect ratios (> 5:1) to facilitate demands of increased interconnect density. Copper (Cu) is a preferred material for TSV filling because of its high electrical and thermal conductivity and can be deposited through electrochemical deposition (ECD) to fill high aspect ratio features. Although Cu ECD has been historically performed using three additive systems, recent work has demonstrated that Cu deposition can be achieved in a simplified CuSO4-H2SO4 electrolyte system with only a single suppressor additive and halide salt.[i],[ii] The cyclic voltammetry (CV) scan for this electrolyte exhibits s-shaped negative differential resistance (S-NDR), observed as hysteresis in the CV voltage-current relationship between forward and reverse scans. Hysteretic voltammetry indicates bifurcating behavior in the electrolyte system, where bottom-up filling is possible in the vias, while the field surface remains passivated. In systems with limited suppression, performing ECD with a sustained potential leads to localized Cu deposition at specific depths within the vias. An increasingly negative potential waveform can be implemented to progressively move deposition vertically through the vias. Achieving a bottom-up, void-free fill with these additive-based electrolytes is typically performed through potentiostatic plating with a reference electrode. Scaling these processes from die level plating experiments, in a small electrochemical cell, to a production-scale full-wafer plating tool requires development of a current-controlled plating regime, because production tools are not equipped with reference electrodes. Furthermore, the developed plating process cannot be highly sensitive to sample rotation rate, because vias at various radial positions across a wafer move at different speeds. In this work, we describe the development of a current-controlled deposition process for bottom-up, void-free filling and further scale this plating process from 1 cm2 sample sizes to a full 150 mm diameter wafer." @default.
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- W3116610080 date "2020-11-23" @default.
- W3116610080 modified "2023-09-26" @default.
- W3116610080 title "Copper Electrodeposition in High Aspect Ratio Mesoscale Through-Silicon Vias: Scaling from Die Level to Wafer Level Plating" @default.
- W3116610080 doi "https://doi.org/10.1149/ma2020-02251787mtgabs" @default.
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