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- W3117103621 abstract "Abstract Inherently small process margins in patterning are a dominant cause of device yield variability, when process conditions or production lines change. This paper highlights the fact that in spite of a perfect lithographic model, the post OPC variation can be substantial due to manufacturing variability. Pattern integrity is a non-intuitive complex mix of manufacturing process practices combined with manufacturable design practices. Failure analysis is the only effective means for filling the understanding gap for yield management in this case. A case study of yield drop due to layout dependent process marginality and a methodical approach to get to the root of the problem are described in this paper." @default.
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- W3117103621 date "2007-11-01" @default.
- W3117103621 modified "2023-09-23" @default.
- W3117103621 title "Photo Process Margin Leading to IC Failure – A Case Study" @default.
- W3117103621 doi "https://doi.org/10.31399/asm.cp.istfa2007p0275" @default.
- W3117103621 hasPublicationYear "2007" @default.
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