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- W3118227685 abstract "This paper presents a cell-based 50% Duty-Cycle Correction (DCC) design supporting a super-wide range of clock frequency from 10MHz to 1.2GHz, using a 90nm CMOS process. It can be integrated with a Delay-Locked Loop (DLL) as a convenient post-processing unit while achieving “zero phase shift” in a way that the phase locking result achieved by its precedent DLL is not affected at all. The unique features in this design include: (1) A wide-range and high-resolution Half-Period Tunable Delay Line (HP-TLD), (2) A fast-locking unit to enable our DCC to lock in to a new incoming clock frequency during frequency scaling, and (3) A wide-range and high-resolution Duty-Cycle Judge (DCJ) circuit as a feedback to guide the overall duty-cycle correction process. Post-layout simulation in a 90nm CMOS process is conducted to validate its effectiveness." @default.
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- W3118227685 date "2020-10-01" @default.
- W3118227685 modified "2023-10-16" @default.
- W3118227685 title "Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz" @default.
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- W3118227685 doi "https://doi.org/10.1109/iccd50377.2020.00083" @default.
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