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- W3118945556 abstract "In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications." @default.
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- W3118945556 date "2013-10-01" @default.
- W3118945556 modified "2023-09-28" @default.
- W3118945556 title "A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER" @default.
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- W3118945556 doi "https://doi.org/10.47893/ijeee.2013.1072" @default.
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