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- W3119205547 abstract "With the development of artificial intelligence, the computing power of the computer is getting higher and higher, which depends on the performance of the processor. The performance of processor is mainly reflected by addition, subtraction, multiplication and division, and multiplier is an important part of it. Therefore, the research and optimization of multiplier is extremely important. In this paper, an 8-bit shift summation multiplier is designed with Verilog programming language. On this base, the multiplier is optimized by the pipeline technology, thus the four-stage pipeline multiplier is realized. After comprehensive wiring on Quartus II 14.1 platform, the ModelSim simulation environment was called to complete the functional simulation, which verified the functional correctness of the multiplier. On the premise of correct functions, the timing simulation was conducted to verify the performance of the multiplier. On the premise of correct functions, the timing simulation was carried out to verify the performance of the multiplier. Through comparative analysis, it can be seen that the speed of the optimized multiplier has been increased by 34.51%, the maximum clock frequency has been increased by one time, and the resource consumption has been reduced by 11.56%." @default.
- W3119205547 created "2021-01-18" @default.
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- W3119205547 date "2020-04-28" @default.
- W3119205547 modified "2023-09-26" @default.
- W3119205547 title "Design and optimization of multiplier base on FPGA" @default.
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- W3119205547 doi "https://doi.org/10.1145/3436286.3436415" @default.
- W3119205547 hasPublicationYear "2020" @default.
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