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- W3120395503 abstract "This project presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. A novel gated-clock-driver tree is then applied to further reduce the activity along the clock distribution network. Moreover, the gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. And also, we are presenting less area over head in this project by using FIFO (First In First Out) technique. FIFO is a technique, which is having the capability to store the DATA with out any write operation and retrieving the DATA without any read operation." @default.
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- W3120395503 date "2012-04-01" @default.
- W3120395503 modified "2023-09-30" @default.
- W3120395503 title "POWER OPTIMIZED MEMORY ORGANIZATION USING GATED DRIVER TREE" @default.
- W3120395503 doi "https://doi.org/10.47893/ijess.2012.1043" @default.
- W3120395503 hasPublicationYear "2012" @default.
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