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• W3123021754 endingPage "104992" @default.
• W3123021754 startingPage "104992" @default.
• W3123021754 abstract "A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design." @default.
• W3123021754 created "2021-02-01" @default.
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• W3123021754 date "2021-03-01" @default.
• W3123021754 modified "2023-10-16" @default.
• W3123021754 title "A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder" @default.
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• W3123021754 doi "https://doi.org/10.1016/j.mejo.2021.104992" @default.
• W3123021754 hasPublicationYear "2021" @default.
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