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• W3125668833 endingPage "045015" @default.
• W3125668833 startingPage "045015" @default.
• W3125668833 abstract "Abstract Herein, we report the low-temperature fabrication process and the electrical response of n-type cadmium sulfide (CdS)-based thin-film transistors (TFTs) with an Al 2 O 3 -GPTMS-polymethylmethacrylate (PMMA) hybrid dielectric gate. The TFTs with bottom-gate structure were assembled on ITO (indium-tin-oxide)-coated glass substrates employing solution processes for the deposition of both the dielectric gate and semiconductor layers. The hybrid dielectric layers were deposited by the sol-gel process and subsequently annealed at 150 °C. The FTIR and XPS analysis of the hybrid films demonstrated a proper link between Al 2 O 3 and PMMA through the cross-linking agent 3-glycidoxy(propyltrimethoxysilane) silane (GPTMS). The surface characteristics were obtained by contact angle and atomic force microscope studies, the results show that the surface of hybrid films displays a hydrophobic behavior with a smooth surface. The CdS active layer was deposited on the hybrid dielectric gate at room temperature by a simple photochemical bath deposition using a 313 nm UV lamp. The CdS-TFTs showed outstanding electrical performance with a low threshold voltage of 1.3 V, I ON /I OFF of 10 4 , subthreshold swing of 440 mV dec −1 , and remarkable high mobility value of 64.4 cm 2 V −1 s −1 . Ultimately, the feature of these completely solution-based CdS TFTs is the maximum processing temperature of 150 °C, and the findings of this study are very promising for potential low-cost solution-processed TFTs." @default.
• W3125668833 created "2021-02-01" @default.
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• W3125668833 date "2021-03-08" @default.
• W3125668833 modified "2023-10-18" @default.
• W3125668833 title "Solution-based CdS thin film transistors with low temperature-processed Al₂O₃-GPTMS-PMMA as hybrid dielectric gate" @default.
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• W3125668833 doi "https://doi.org/10.1088/1361-6641/abe01c" @default.
• W3125668833 hasPublicationYear "2021" @default.
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