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• W3126555455 abstract "Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh interconnect, which consists of a network-on-chip interconnecting “tiles”, each of which contains computation cores, local caches, and coherence masters. The distributed coherence subsystem must be queried for every out-of-tile access, imposing an overhead on memory latency. This paper studies the physical layout of an Intel Knights Landing processor, with a particular focus on the coherence subsystem, and uncovers the pseudo-random mapping function of physical memory blocks across the pieces of the distributed directory. Leveraging this knowledge, candidate optimizations to improve memory latency through the minimization of coherence traffic are studied. Although these optimizations do improve memory throughput, ultimately this does not translate into performance gains due to inherent overheads stemming from the computational complexity of the mapping functions." @default.
• W3126555455 created "2021-02-15" @default.
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• W3126555455 date "2021-01-01" @default.
• W3126555455 modified "2023-10-17" @default.
• W3126555455 title "Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings" @default.
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• W3126555455 doi "https://doi.org/10.1109/access.2021.3058280" @default.
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