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- W3126562005 abstract "Empirical thesis.%%%%%%%%Bibliography: pages 261-284.%%%%1. Introduction – 2. Background – 3. Counter-based Wallace multipliers – 4. Modular multiplier using sum of residues in RNS – 5. Chip fabrication for RNS-based modular multiplier – 6. Elliptic curve point multiplication – 7. Conclusions and future work.%%%%This thesis presents designs and hardware implementations of modular arithmetic for elliptic curve point multiplication (ECPM). The aim is to speed up elliptic curve cryptography (ECC) architectures and optimise their power consumption. Improvements are made in existing algorithms, and conventional number systems are replaced by residue number systems (RNS) to achieve a high speed for basic arithmetic operations. The proposed ECPM architectures are generic and can be scaled for different key sizes; the hardware implementations in this work are for 256-bit ECPM over prime field Fp.%%%%ECPM architectures are optimised in two ways. Firstly, three different hardware architectures are developed for the implementation of an efficient modular multiplier (MM). These architectures, named parallel, serial, and serial-parallel, offer a trade-off between area and delay. The performance of the proposed MM architectures is compared, based on their ASIC (Application Specific Integrated Circuit) and FPGA (Field Programmable Gate Array) implementation results. Moreover, the feasibility of serial MM architecture for practical implementation is proved by its ASIC fabrication using 65 nm CMOS technology. The measurement results for the fabricated chip show that the proposed MM is better than other state-of-the-art MM architectures.%%%%Secondly, two ECPM architectures, named multi-key ECPM and single-key ECPM, are proposed; they differ in terms of throughput and hardware complexity. Multi-key ECPM provides a high throughput by processing twenty one keys simultaneously within deep pipeline stages. Single-key ECPM attempts to optimise the hardware cost by resource sharing. Power optimisation techniques are employed to reduce the power consumption of the single-key ECPM. The proposed architectures are implemented on FPGA and ASIC platforms and the results are analysed to discuss the suitability of the proposed ECPM architectures for different applications.%%%%%%%%1 online resource (xxviii, 284 pages) colour illustrations" @default.
- W3126562005 created "2021-02-15" @default.
- W3126562005 creator A5087018800 @default.
- W3126562005 date "2016-01-01" @default.
- W3126562005 modified "2023-10-02" @default.
- W3126562005 title "High-speed low-power modular arithmetic for elliptic curve cryptosystems based on the residue number system" @default.
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