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- W3126817144 abstract "This paper proposes a phase synchronization technique between multiple fractional-N PLLs. By matching an operating state of a DSM, which is driven by a multi-modulus divider (MMD) output, and that of a Reference DSM, which is driven by a reference clock, phase error between PLLs can be removed. The proposed PLL was fabricated in a 0.13um SiGe BiCMOS process, and successfully removed a phase variation between two PLLs." @default.
- W3126817144 created "2021-02-15" @default.
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- W3126817144 date "2020-12-08" @default.
- W3126817144 modified "2023-09-27" @default.
- W3126817144 title "Phase Synchronization Technique Between Fractional-N PLLs by Correcting Phase Error due to Cycle Slip using Reference Delta-Sigma Modulator" @default.
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- W3126817144 doi "https://doi.org/10.1109/apmc47863.2020.9331543" @default.
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