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W3127483746 abstract "In this article, we analyzed the stability, power, performance, and area of 6T-SRAMs using a promising scaling booster, i.e., source/drain patterning (SDP) scheme for the 3-nm technology node based on 3-D TCAD simulation. SDP scheme allows to decrease the spacing between transistors by downsizing the source/drain epitaxy. Proposed 5-nm and 3-nm SDP-SRAM (SDP-SRAM 5 and SDP-SRAM 3 ) are compared with conventional 5-nm node SRAM (Conv-SRAM 5 ), quantitatively. Unlike a Conv-SRAM 5 , SDP-SRAMs have more design margins according to the two fin position parameters: fin location adjustment (FLA) and separation pitch adjustment (SPA). The optimized layout has the maximum FLA by significantly decreasing the back-end-of-line (BEOL) bitline and internal node capacitance. Read and write static noise margins were comparable (<; 10 mV) between the SDP-SRAM and Conv-SRAM. The SDP-SRAM 5 improved the read access time 18% compared to the Conv-SRAM 5 in low-power (LP) applications, but the SDP-SRAM 3 degraded it by 11% in high-performance (HP) applications because of the narrow M2 pitch. Both the SDP-SRAM 5 and SDP-SRAM 3 improved write access time about 10% compared to a Conv-SRAM 5 in LP applications. The cell area of the SDP-SRAM 3 decreased about 0.64 times compared to a Conv-SRAM 5 without severe degradation of performance. The SDP scheme provides flexible layout designs enabling a high-density SRAM, promising for 3-nm node logic applications." @default.
W3127483746 created "2021-02-15" @default.
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W3127483746 date "2021-03-01" @default.
W3127483746 modified "2023-10-14" @default.
W3127483746 title "TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme" @default.
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W3127483746 doi "https://doi.org/10.1109/ted.2021.3053508" @default.
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