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- W3127575539 abstract "This paper presents a systematic study on the performance of double gate (DG)-MOSFETs with an ultrathin embedded dielectric film (DF) at the center of the channel from the source to drain of the device. The numerical simulation results show that for k ≤ 12, the value of ION/IOFF of a 20-nm DF-DG-MOSFET increases with increasing value of DF thickness t reaching a maximum value of about 107 for dielectric constant k = 1, and t = 5 nm whereas, tends to decrease for k > 12. Also, the 20 nm DF-DG-MOSFET with (k = 1, t = 5 nm) shows the lowest subthreshold swing SS of 79 mV/decade and drain induced barrier lowering DIBL of 109 mV/V. However, the intrinsic delay of DF-DG-MOSFET increases with increasing t for k ≤ 12, whereas, decreases as both t and k increase for k > 12 reaching a value of 0.5 ps for (k = 80, t = 5 nm) compared to 0.8 ps for an identical conventional DG-MOSFET. This study, clearly, shows that the performance of DG-MOSFETs can be optimized by wise choice of t and k of an embedded DF and provides guidelines for the design of high performance and low power nanoscale logic devices." @default.
- W3127575539 created "2021-02-15" @default.
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- W3127575539 date "2021-03-01" @default.
- W3127575539 modified "2023-10-16" @default.
- W3127575539 title "Design and analysis of ultra-thin dielectric film embedded nanoscale double-gate MOSFETs for boosting logic performance" @default.
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- W3127575539 doi "https://doi.org/10.1016/j.aeue.2021.153614" @default.
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