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• W3129323610 endingPage "106980" @default.
• W3129323610 startingPage "106980" @default.
• W3129323610 abstract "DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a difficult task due to its low-frequency nature. This paper proposes a method to remove the DC-offset in the single-phase grid synchronization utilizing delay signal cancellation (DSC) and a variable-length time delay (VLTD) based PLL. The small-signal model, stability analysis, and controller gains selection are discussed. The proposed PLL is compared with other single-phase PLLs in terms of the phase settling time, the phase percent maximum overshoot, and the peak of the estimated frequency, to show its advantages." @default.
• W3129323610 created "2021-03-01" @default.
• W3129323610 creator A5007206975 @default.
• W3129323610 creator A5062585842 @default.
• W3129323610 date "2021-05-01" @default.
• W3129323610 modified "2023-10-16" @default.
• W3129323610 title "Phase-locked loop with DC offset removal for single-phase grid-connected converters" @default.
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• W3129323610 doi "https://doi.org/10.1016/j.epsr.2020.106980" @default.
• W3129323610 hasPublicationYear "2021" @default.
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