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- W3133788077 abstract "A 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with 20dB loss compensation is proposed in a 65nm CMOS technology. The receiver employs a quad-rate hybrid DFE architecture to reduce power consumption. DFE can halve the number of summers by adding reset to slicer, and multiplexer to the summer. In the proposed DFE, 7Gb/s data converted to digital signals by the slicer and IIR filter are added at the summer, and d flip flop sends a signal that the noise has been removed to the output. Because slicer and summer are implemented to operate at high speed, the proposed DFE doesn't require the sample-and-hold (S/H). So, the DFE has a simple structure and operates at high speed with low power consumption. The proposed DFE occupies 0.023mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and power consumption is 18.2mW with 1.2V supply voltage." @default.
- W3133788077 created "2021-03-15" @default.
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- W3133788077 date "2021-01-31" @default.
- W3133788077 modified "2023-09-25" @default.
- W3133788077 title "A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process" @default.
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- W3133788077 doi "https://doi.org/10.1109/iceic51217.2021.9369760" @default.
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