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- W3134865440 abstract "The interface trap charges (ITC) associated reliability analysis of a charge-plasma based asymmetric double-gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high-κ gate dielectric (HJADGDLTFET) has been studied. The HJADGDLTFET uses silicon at the drain and the channel region, and germanium at the source region, which enhances the band-to-band tunnelling at the source-channel junction, and hence drive current is increased by one order concerning ADGDLTFET. Also, ADG and high-κ dielectric (HfO2) have been used to maintain low off-state current values. The primary intention of this work is to investigate the impact of ITC for HJADGDLTFET and compare it for ADGDLTFET considering DC, analog/RF, and linearity parameters such as transfer characteristics, electric-field, electric potential, first-, second-, and third-order transconductances (gm1, gm2, and gm3), gate-to-drain capacitance (Cgd), cut-off frequency (fT), gain–bandwidth product, device efficiency, second- and third-order voltage intercept points (VIP2, VIP3), third-order input intercept points (IIP3), and third-order intermodulation distortion. The ATLAS simulation results show that the HJADGDLTFET is more immune to ITC variation than conventional ADGDLTFET concerning different polarities of ITC available at the semiconductor-oxide interface." @default.
- W3134865440 created "2021-03-15" @default.
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- W3134865440 date "2021-02-28" @default.
- W3134865440 modified "2023-10-17" @default.
- W3134865440 title "Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET" @default.
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- W3134865440 doi "https://doi.org/10.1049/cds2.12037" @default.
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