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- W3135707024 abstract "This paper presents a new dc-link capacitor voltage balancing method for three-level Space Vector Modulation (SVM) strategies that are based on the space vector diagram of two-level inverters. The proposed method uses the time distribution of the local two-level zero vectors to achieve dc- link voltage balancing. It redistributes the zero vector times based on the magnitude and direction of the dc-link capacitor voltage deviations. The performance of the proposed capacitor voltage balancing method is compared with the conventional three-level SVM capacitor voltage balancing method that uses three-level redundant small vectors. The proposed method achieves significantly lower neutral-point voltage ripple compared to the conventional three-level SVM capacitor voltage balancing method for a wide range of modulation indices and load power factor values. Moreover, the code size and execution time are reduced by approximately 30 percent for use in microcontrollers." @default.
- W3135707024 created "2021-03-15" @default.
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- W3135707024 date "2020-11-29" @default.
- W3135707024 modified "2023-10-18" @default.
- W3135707024 title "A New Dc-link Capacitor Voltage Balancing Method for Three-level SVM Strategies Based on Two-level Space Vector Diagram" @default.
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- W3135707024 doi "https://doi.org/10.1109/ipemc-ecceasia48364.2020.9367733" @default.
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