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- W3136303866 abstract "Boolean equivalence checking has turned out to be a powerfulmethod for verifying combinatorial circuits and has been widelyaccepted both in academia and industry.In this paper, we present a method for localizing and correctingerrors in combinatorial circuits for which equivalence checkinghas failed. Our approach is general and does not assume anyerror model. Working directly on BDDs, the approach is wellsuited for integration into commonly used equivalence checkers.Since circuits can be corrected fully automatically, ourapproach can save considerable debugging time and thereforewill speed up the whole design cycle.We have implemented a prototype verification tool and evaluatedour method with the Berkeley benchmark circuits. In addition, wehave applied it successfully to a real life example taken from[DrFe96]." @default.
- W3136303866 created "2021-03-29" @default.
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- W3136303866 date "1999-01-01" @default.
- W3136303866 modified "2023-09-23" @default.
- W3136303866 title "Using BDD-based decomposition for automatic error correction of combinatorial circuits" @default.
- W3136303866 doi "https://doi.org/10.5445/ir/9699" @default.
- W3136303866 hasPublicationYear "1999" @default.
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