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- W3137449056 abstract "This paper presents low leakage and high speed 1-bit full adder projected with low threshold NMOS transistors in associations with universal logic gates which leads to have reduced power and delay. The customized NAND and NOR gates, a necessary blocks, are presented to design a proposed adder cell. The simulations for the designed circuits performed in cadence virtuoso tool with 65 nm CMOS technology at a supply voltage of 1 Volts. The proposed universal gates and 1-bit adder cell is compared with conventional NAND/NOR gates and 1-bit adder. The proposed adder schemes with modified universal logic gates achieve significant saving in terms of delay which are more than 24% and which is at the cost of 5% when compared with conventional designs." @default.
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- W3137449056 date "2021-01-28" @default.
- W3137449056 modified "2023-10-01" @default.
- W3137449056 title "Leakage Reduction Methodology in CMOS for the Design of 1-Bit Full Adder" @default.
- W3137449056 doi "https://doi.org/10.46647/ijetms.2021.v05i01.001" @default.
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