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• W3140877430 abstract "An approach to top down design for testability using register-transfer level (RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented." @default.
• W3140877430 created "2021-04-13" @default.
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• W3140877430 date "2002-11-19" @default.
• W3140877430 modified "2023-09-27" @default.
• W3140877430 title "Design for testability using register-transfer level partial scan selection" @default.
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• W3140877430 doi "https://doi.org/10.1109/aspdac.1995.486225" @default.
• W3140877430 hasPublicationYear "2002" @default.
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