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- W3140993944 abstract "The addition of programmable logic to RISC machines has the potential of exploiting the inherent parallelism of hardware to speedup an application. In this paper, we study the effect of adding a programmable accelerator to DLX, a RISC prototype. We build this model and parameterize the communication overhead between the processor and programmable unit and logic/routing delays inside the programmable unit. We use simulation to evaluate the performance of this model, parameterized by comm,unication overhead and logic delays, by comparing it with the baseline DLX architecture on some sample problems. Our methodology is useful an studying the relative importance of the parameters and in projecting the performance of the system, if the programmable logic were to be implemented inside the processor." @default.
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- W3140993944 date "1996-12-01" @default.
- W3140993944 modified "2023-09-23" @default.
- W3140993944 title "A Quantitative Analysis of Processor - Programmable Logic Interface" @default.
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