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- W3142446421 abstract "The very large scale integration (VLSI) community has utilized aggressive complementary metal-oxide semiconductor (CMOS) technology scaling to meet the everincreasing performance requirements of computing systems. However, as we enter the nanoscale regime, the prevalent process variation effects degrade the CMOS device reliability. Hence, it is increasingly essential to explore emerging technologies which are compatible with the conventional CMOS process for designing highly-dense memory/logic circuits. Memristor technology is being explored as a potential candidate in designing non-volatile memory arrays and logic circuits with high density, low latency and small energy consumption. In this thesis, we present the detailed functionality of multi-bit 1-Transistor 1-memRistor (1T1R) cell-based memory arrays. We present the performance and energy models for an individual 1T1R memory cell and the memory array as a whole. We have considered TiO2and HfOx-based memristors, and for these technologies there is a sub-10% difference between energy and performance" @default.
- W3142446421 created "2021-04-13" @default.
- W3142446421 creator A5016699520 @default.
- W3142446421 creator A5061693990 @default.
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- W3142446421 date "2014-01-01" @default.
- W3142446421 modified "2023-09-24" @default.
- W3142446421 title "Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors" @default.
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- W3142446421 hasPublicationYear "2014" @default.
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