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• W3143257989 abstract "This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit variations and most papers on data-path circuit optimization disregard clock tree variation, we consider both. Using both clock and data-path variations together, we present a novel sensitivity-matching algorithm that allows clock tree skews to be intentionally correlated with data-path sensitivities to ameliorate timing violations due to variation. Our statistical tuning shows an improvement in terms of expected clock skew and clock skew variation over previously published robust algorithms." @default.
• W3143257989 created "2021-04-13" @default.
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• W3143257989 date "2008-01-01" @default.
• W3143257989 modified "2023-09-25" @default.
• W3143257989 title "Clock tree synthesis with data-path sensitivity matching" @default.
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• W3143257989 doi "https://doi.org/10.1109/aspdac.2008.4484001" @default.
• W3143257989 hasPublicationYear "2008" @default.
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