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- W3144707992 abstract "The problem of determining bounds for application completion times running on generic systems comprised of single or multiple voltage-frequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-driven variability. The approach provides an exact solution for the system-level timing yield in single clock, single voltage (SSV) and VFI systems with an underlying tree-based topology, and a tight upper bound for generic, non-tree based topologies. The results show that: (a) timing yield for overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems; and (b) multiple VFI, latency-constrained systems can achieve 11-90% higher timing yield than their SSV counterparts. The results are proven formally and supported by experimental results on two embedded applications, namely software defined radio and MPEG2 encoder" @default.
- W3144707992 created "2021-04-13" @default.
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- W3144707992 date "2006-11-01" @default.
- W3144707992 modified "2023-09-26" @default.
- W3144707992 title "System-Level Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island Systems" @default.
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- W3144707992 doi "https://doi.org/10.1109/iccad.2006.320171" @default.
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