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- W3144971646 abstract "Frequency-fixed implementation of a single-phase frequency-locked loop (FLL) has been reported to enhance the FLL's dynamic performance when the supply voltage is sinusoidal or harmonically distorted. However, when dc-offset is present in the supply voltage, a dc-offset rejection (DC-OR) stage is usually incorporated in the FLL implementation. How the DC-OR stage affects the FLL's dynamic performance is one gap that exists in the literature. Consequently, this paper focuses on evaluating the effect of the DC-OR stage on the FLL's performance by coupling and decoupling the DC-OR stage and the FLL. Decoupling is achieved by fixing the frequency of the DC-OR stage at the supply voltage's nominal frequency. However, this introduces a phase-offset error at the FLL output when the supply voltage experiences a frequency deviation. To address this issue, a phase-offset compensation approach is developed. Through experimental studies, accuracy of the phase-offset compensation approach is verified. Furthermore, it is shown that farther the point of decoupling and the FLL output, faster is the FLL response. Therefore, a frequency-adaptive FLL can achieve faster response than its frequency-fixed counterpart when the effect of dc-offset rejection stage is considered." @default.
- W3144971646 created "2021-04-13" @default.
- W3144971646 creator A5025206245 @default.
- W3144971646 creator A5038773668 @default.
- W3144971646 date "2020-12-16" @default.
- W3144971646 modified "2023-09-26" @default.
- W3144971646 title "DC-Offset Rejection Approaches for Single-Phase Frequency-Locked Loop" @default.
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- W3144971646 doi "https://doi.org/10.1109/pedes49360.2020.9379567" @default.
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