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• W3147171055 abstract "Summary This paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents I o n , at least one order lower off currents I o f f , twice the transconductance g m , at least two orders higher output resistance r o , and at least two orders higher overall intrinsic gain g m r o than the equivalent metal‐oxide‐semiconductor field‐effect transistor (MOSFET) having the same width at the same technology node. The proposed device, being a double‐gate (DG) structure, exhibits extremely high vertical fields which ensures that line‐tunneling dominates over the point‐tunneling by several orders. This eliminates the notorious “hump” or the “kink” effects observed in conventional LTFET characteristics, which are detrimental for analog applications. In this work, we have optimized the DGLTFET device by changing critical parameters like the epi‐layer thickness and its doping concentration, which have serious influence on the line‐tunneling behavior. Optimization of the critical parameters for enhanced line‐tunneling leads to improved analog performance parameters like g m and r o , and finally, superior analog circuits. The performance of the DGLTFET was benchmarked with the equivalent MOSFET in fundamental analog VLSI circuits, namely, CS amplifier (both resistive and cascode loads), current mirror (both single‐stage and cascode configurations), and a two‐stage op‐amp. This paper shows that the DGLTFET CS amplifier has a gain‐BW product or unity‐gain BW f T of 15 GHz, while that of MOSFET CS amplifier with the same bias current is 10 GHz. The DGLTFET current mirror has at least three orders of magnitude higher r o than the corresponding MOSFET current mirror. Similarly, the common‐mode rejection ratio (CMRR) of the DGLTFET op‐amp is 57 dB compared to the CMRR of 33.5 dB of the equivalent design in standard 45‐nm complementary metal‐oxide semiconductor (CMOS) technology. The 45‐nm library is the lowest industry‐standard technology node currently available free for academic licenses in the public domain; hence, the benchmarking for validation was carried out at 45 nm. However, the claims/investigations made in this work are also valid for lower technologies, and related results are excluded in this report keeping the manuscript length in mind." @default.
• W3147171055 created "2021-04-13" @default.
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• W3147171055 date "2021-04-01" @default.
• W3147171055 modified "2023-10-17" @default.
• W3147171055 title "Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance" @default.
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• W3147171055 doi "https://doi.org/10.1002/cta.3002" @default.
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