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- W3147272621 abstract "We present a scheme for optimal VLSI layout and packaging of butter y networks under the Thompson model, the multilayer grid model, and the hierarchical layout model. We show that when L layers of wires are available, an N node butter y network can be laid out with area 4N 2 L2 log2 2 N + o N L2 log2 N , maximum wire length 2N L log2 N + o N L logN , and volume 4N 2 L log2 2 N +o N L log2 N , under the multilayer 2-D grid model, where only one active layer (for network nodes) is required and L layers of wires are available. Our layout scheme allows us to partition an N -node butter y network into (N log N)-node clusters with an average of dic 4l 4 log2 N (= O( 1 logN ) for any constant integer l) intercluster links per node, leading to optimal layout and packaging at the same time under the hierarchical layout model. The scalability of our layouts are optimal in that we can allow each of O(N= logN) nodes to occupy an area as large as o N L2 logN and each of the remaining N o(N) network nodes to occupy an area as large as o N L2 log2 N , without increasing the leading constants of layout area, volume, or maximum wire length." @default.
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- W3147272621 date "2000-01-01" @default.
- W3147272621 modified "2023-09-23" @default.
- W3147272621 title "VLSI Layout and Packaging of B utterfly N etw orks" @default.
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