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- W3147988478 abstract "This paper aims in implementation of DRC rules in TSMC 0.18 µm PDK. The main focus is on methodology employed to implement rules for optimization with respect to area and delay of the circuit under design. PDK consists of foundry specific rule files which are used in electronic design automation (EDA) tools. A prominent step in chip design process is physical verification of the layout for a particular circuit. It is critical to verify that the layout does not violate any design rules, and that it matches the schematic design. The DRC rule deck focuses on primitive rules such as spacing between different tracks and minimum widths. This work focuses on implementation of different rules such as metal width, poly, and contact and via placement which do not exist in the rule deck. Standard verification rule format (SVRF) manual is referred while writing snippets for different rules. Rules are written for TSMC 0.18 µm technology and are verified in Mentor Graphics Calibre tool." @default.
- W3147988478 created "2021-04-13" @default.
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- W3147988478 date "2021-01-01" @default.
- W3147988478 modified "2023-09-24" @default.
- W3147988478 title "Implementation of Custom DRC in TSMC 0.18 µm for Optimized Layout" @default.
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- W3147988478 doi "https://doi.org/10.1007/978-981-33-4866-0_59" @default.
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